The present invention relates to the fabrication of integrated circuits. Some specific embodiments of the invention pertain to a method for forming a dual damascene structure in an integrated circuit in which the etched dielectric layer(s) include one or more porous low dielectric constant films.
As semiconductor device sizes have become smaller and integration density increases, many issues have become of increasing concern to semiconductor manufacturers. One such issue is that of interlevel xe2x80x9ccrosstalk.xe2x80x9d Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer, and arises when two or more layers of metal with intervening insulating or dielectric layers are formed on a substrate. Crosstalk can be reduced by moving the metal layers further apart, minimizing the areas of overlapping metal between metal layers, reducing the dielectric constant of the material between metal layers and combinations of these and other methods. Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer. As device geometries shrink, the conductive lines become closer together and it becomes more important to better isolate them from each other.
Another such issue is the xe2x80x9cRC time constantxe2x80x9d of a particular trace. Each conductive trace has a resistance, R, that is a product of its cross section and bulk resistivity, among other factors, and a capacitance, C, that is a product of the surface area of the trace and the dielectric constant of the material or the space surrounding the trace, among other factors. If a voltage is applied to one end of the conductive trace, charge does not immediately build up on the trace because of the RC time constant. Similarly, if a voltage is removed from a trace, the trace does not immediately drain to zero. Thus high RC time constants can slow down the operation of a circuit. Unfortunately, shrinking circuit geometries produce narrower traces, which results in higher resistivity. Therefore it is important to reduce the capacitance of the trace, such as by reducing the dielectric constant of the surrounding material between traces, to maintain or reduce the RC time constant.
Hence, in order to further reduce the size of devices on integrated circuits, it has become necessary to use insulators that have a lower dielectric constant than the insulators of previous generations of integrated circuits. To this end, semiconductor manufacturers, materials suppliers and research organizations among others have been researching and developing materials for use as premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers in integrated circuits that have a dielectric constant (k) below that of silicon dioxide (generally between about 3.9-4.2) and below that of fluorine-doped silicate glass (FSG, generally between about 3.4-3.7). These efforts have resulted in the development of a variety of low dielectric constant films (low k films). As used herein, low k films are those having a dielectric constant less than about 3.0 including films having a dielectric constant below 2.0.
Some approaches to developing such low k films include introducing porosity into known dielectric materials to reduce the material""s dielectric constant. Dielectric films when made porous, tend to have lower dielectric constants (the dielectric constant of air is normally 1.0). One particular class of porous low k films includes ordered mesoporous silica materials. One known method of forming such ordered mesoporous silica films is referred to as the sol gel process, in which high porosity films are produced by hydrolysis and polycondensation of a metal oxide.
The sol gel process is a versatile solution process for making ceramic material. In general, the sol gel process involves the transition of a system from a liquid xe2x80x9csolxe2x80x9d (mostly colloidal) into a solid xe2x80x9cgelxe2x80x9d phase. The starting materials used in the preparation of the xe2x80x9csolxe2x80x9d are usually inorganic metal salts or metal organic compounds such as metal alkoxides. The precursor solutions are typically deposited on a substrate by spin on methods. In a typical sol gel process, the precursor is subjected to a series of hydrolysis and polymerization reactions to form a colloidal suspension, or a xe2x80x9csol.xe2x80x9d Further processing of the xe2x80x9csolxe2x80x9d enables one to make ceramic materials in different forms. One method of forming such mesoporous low k films is described in U.S. application Ser. No. 09/823,932, filed on Mar. 29, 2001 in the name of Robert P. Mandel et al. and assigned to Applied Materials, Inc., the assignee of the present case. The Ser. No. 09/823,932 application is hereby incorporated by reference in its entirety.
Concurrent with the move to intermetal dielectric layers having a dielectric constant lower than silicon dioxide, many semiconductor manufacturers are using copper rather than aluminum in the formation of their multilevel interconnect structures. Because copper is difficult to etch in a precise pattern, however, the traditional deposition/selective etch process used for forming such interconnects has become disfavored. Accordingly, a process referred to as a dual damascene process, is used by many semiconductor manufacturers to form copper interconnects. In a dual damascene process, one or more blanket intermetal dielectric layers are deposited and then subsequently patterned and etched to define both the interlayer vias and the interconnect lines. Copper or another conductive material is then inlaid into the defined pattern and any excess conductive material is removed from the top of the structure in a planarization process, such as a chemical mechanical polishing (CMP) process.
The etching of the dielectric layer in such a dual damascene process typically includes two separate lithography steps. One step defines the trenches and another the vias. Photoresist and organic bottom antireflective coating (BARC) films have been found to penetrate the pores of porous low k films so dual damascene lithography techniques for porous low k films typically include the use of a hard mask between the ELK material and the photoresist. One such scheme that has been proposed includes the use of two separate hard masks as shown in FIGS. 1a through 1h. 
FIGS. 1a through 1h illustrate one method used in the fabrication of a trench-first dual damascene scheme using a silicon-containing dielectric layer 10 formed over a substrate 2. Substrate 2 may include an already formed conductive line 4, e.g., a copper line, a surrounding dielectric material 6 and a barrier layer separating the two. Dielectric layer 10 may be a single layer or a multilayer dielectric stack. Dielectric layer 10 shown in FIG. 1a includes multiple layers: a barrier layer 12, a via dielectric layer 14 and a porous low k layer 16. Formed over dielectric layer 10 are a first hard mask layer 20, a second hard mask layer 22, a bottom antireflective coating 24 and a photoresist layer 30. In some prior processes known to the inventors where the trench and via portion of underlying dielectric layer 10 are a silicon-containing material, hard mask layer 22 is a silicon nitride or similar layer and layer 20 is a silicon carbide (SiC or SiCN) or similar layer.
As shown in FIG. 1a photoresist layer 30 is patterned and etched using a metal wiring pattern to form an opening 32. The metal wiring pattern is then transferred into hard mask layer 22 using an appropriate etching process (FIG. 1b). Any remaining photoresist layer 30 is then stripped along with antireflective coating 24 (FIG. 1c). Next, a new bottom antireflective coating 40 and photoresist layer 42 is formed over the substrate such that antireflective coating 40 fills in etched opening 32 (FIG. 1d).
As shown in FIG. 1d, photoresist layer 42 is then patterned and etched according to a via pattern to form an opening 34. The via pattern is then transferred into dielectric stack 10 using photoresist layer 42 as the pattern (FIG. 1e) and afterwards, photoresist layer 42 and antireflective layer 40 are stripped leaving a partially formed via 50 and a larger opening 32 (FIG. 1f). Next, the desired trench 52 and via 50 are etched into low k dielectric layer 10 (FIG. 1g) and barrier layer 12 is etched through to complete the etched via formation (FIG. 1h). Once the formation of via hole 50 and trench 52 are completed, the structure can be filled with copper or another conductive material. The filled structure is then subjected to a planarization step, such as a CMP step, to complete the formation of the interconnect structure. In the completed structure the top of the just-formed conductive line is essentially even with the top of dielectric layer 10.
While the above described process can be used to successfully form dual damascene structures for some integrated circuits, it is not without its limitations. For example, in some applications hard mask layer 22 is required to have a thickness in the range of 1500 xc3x85 to 5000 xc3x85 in order to remain in place during the etching steps shown in FIGS. 1f, 1g and 1h. Such a relatively thick layer is required for the scheme because etch chemistry selectivity issues and physical sputtering. If the layer is too thin, it will be etched entirely away during the etching steps shown in FIGS. 1f-1h, which in turn may cause the complete loss of hard mask layer 20 during the subsequent CMP process. The loss of hard mask layer 20 during CMP may in turn cause the CMP slurry to intrude into the porous low k dielectric material causing material and defect issues. Similarly, hard mask layer 22 is subject to sputtering effects during the etching processes shown in FIGS. 1f-1h. If the layer is too thin, such sputtering may result in the corner chopping and critical dimension loss in the underlying etched features (via 50 and trench 52). This in turn may result in shorting of conductive lines and/or other problems.
The requirement of such a relatively thick hard mask layer 22 however leads to lithography issues. For example, via opening 34 is patterned inside, or at least partially inside, previously etched and subsequently filled opening 32. The topography created by this hard mask trench etch/fill process may present depth of focus issues during the subsequent lithography process of photoresist layer 42. This is especially true as such dual damascene schemes for low k films are expected to be used in processes that include minimum feature sizes of 0.15 microns and smaller thereby using radiation wavelengths of 193 nm or less for the lithography steps.
FIG. 2, is a simplified cross-sectional drawing of a substrate showing the possible topography of antireflective layer 40 and photoresist layer 42 just prior to the etching of opening 34 shown in FIG. 1d. Photoresist layer 42 includes areas 60 that are to be developed by exposing the corresponding portions of the photoresist layer to appropriate radiation. As shown in FIG. 2, antireflective coating 40 is generally not planar having a recessed portion 62 in an area corresponding to particularly large opening 32 of hard mask layer 22 and raised portions 64 corresponding to areas of the substrate having small trenches or no trenches at all. The uneven topography of layer 40 results in a similarly uneven topography for photoresist layer 42 and a height difference 70 between the top surface of layer 42 in areas 64 as compared to the top of layer 42 in area 62.
The size of height difference 70 is in part due to the thickness of hard mask layer 22. A thinner hard mask layer 22 enables the formation of more planar layers 40 and 42. When height difference 70 is greater than or close to the depth of focus (DOF) of the radiation used to pattern layer 42, portions of layer 42 may not be properly exposed during the patterning process. This, in turn, may result in underdeveloped photoresist and incorrectly dimensioned vias and/or vias that are not opened uniformly all across the wafer.
Additionally, there is an etching issue with this scheme. For vias located in region 64, the portion of antireflective coating 40 that needs to be etched during the via etch step (FIG. 1E) is thicker than the portion of layer 40 that needs to be etched for vias in region 62. As a result, the etched via depth may differ in the two regions which can cause low via yield and reliability issues.
Accordingly, it can be seen that improvements and/or alternative schemes for forming dual damascene structures using porous low dielectric constant films are desirable.
Embodiments of the present invention pertain to a method for forming a dual damascene structure in an integrated circuit. Some embodiments of the invention minimize the thickness of the hard mask structure used to pattern a dual damascene structure by employing an amorphous silicon layer as the second layer of the hard mask structure. Such a layer can provide a higher etch selectivity to the silicon-containing trench and/or via dielectric material etched in damascene processes than provided by some previously used hard mask layers. Higher etch selectivity allows for a thinner hard mask layer, which in turn, reduces the photoresist development and via etch problems associated with some previously known processes.
One embodiment of the method of the invention forms a dual damascene structure on a substrate having a dielectric layer already formed thereon by depositing a first hard mask layer over the dielectric layer and depositing an amorphous silicon hard mask layer on the first hard mask layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material. In one embodiment the amorphous silicon material includes between 70-90 atomic percent silicon and 10-30 atomic percent hydrogen.
In some embodiments, the dielectric layer comprises inorganic silicon-containing trench and/or via dielectric portions and the metal wiring and via patterns are etched into the layer using a fluorine-containing plasma that exhibits an etch selectivity of at least 6:1 between the dielectric material being etched and the amorphous silicon hard mask layer. In some specific embodiments the inorganic silicon-containing trench dielectric layer is a porous oxide film deposited by spin-on methods and the inorganic silicon-containing via dielectric layer is a carbon-doped silica glass film deposited by chemical vapor deposition (CVD) techniques.
According to another embodiment of the method of the invention, a dual damascene structure is formed over a substrate having a first interconnect layer already formed thereon. The method forms a barrier dielectric layer over the first interconnect layer and forms a silicon-containing via dielectric layer over the barrier dielectric layer. Next, a silicon-containing porous low dielectric constant layer is formed over the via dielectric layer and first and second hard mask layers are formed over the porous low dielectric constant layer, respectively, where the second hard mask layer is an amorphous silicon material. A first antireflective coating is then formed over the second hard mask layer. A photoresist layer is then formed over said the antireflective coating and patterned in accordance with a metal wiring pattern to expose selected portions of the first antireflective coating. The metal wiring pattern is then transferred into the first antireflective layer and the second hard mask layer using appropriate etching processes and then the photoresist layer and the first antireflective coating are removed with an appropriate stripping process. Afterwards, a second antireflective coating and then second photoresist layer are formed over the patterned second hard mask layer. The second photoresist layer is patterned in accordance with a via pattern to expose selected portions of the second antireflective coating, and then a via hole is etched through the second antireflective coating, through the second and first hard mask layers and into at least a portion of the porous low dielectric constant layer. The second photoresist layer and second antireflective coating are then removed using an appropriate stripping process and the metal wiring pattern is etched into the porous low dielectric constant layer while the via pattern is transferred into the via dielectric layer. Finally, the barrier dielectric layer is opened in the via to expose portions of the first interconnect layer and the etched via and trench are filled with a conductive material.
These and other embodiments of the present invention, as well its advantages and features, are described in more detail in conjunction with the description below and attached figures.